The invention relates to a synchronization circuit for handling and synchronizing a write operation on a semiconductor memory, particularly a DDR graphics memory.
In modern computer and software applications, there is increasingly the need to process ever greater volumes of data in ever shorter times. The data are stored using large-scale integrated memories, such as DRAM stores. In order to comply with the need for ever greater speed when processing data, the data need to be written to the memory and read from this memory again at corresponding speed. This can be implemented, by way of example, at an ever increasing operating frequency which can be used to read or write the data from or to a semiconductor memory.
Another option is to use semiconductor memories designed specifically for high data rates. One representative of such a semiconductor memory is what is known as the “DDR-DRAM” store, with DDR standing for “Double Data Rate”. Although they may be applied to any semiconductor memories, the present invention and its underlying problems are explained below with reference to DDR-DRAM semiconductor memories and, in this case, particularly to graphics memories of this kind. Whereas, in conventional semiconductor memories, read and write operations are carried out only upon the rising or upon the falling edge of a clock signal, data in the case of the said DDR semiconductor memories are read from the semiconductor memory and written back to the memory both upon the rising edge and upon the falling edge of a clock signal. These semiconductor memories are therefore distinguished by a double data rate.
Future DDR graphics memories from the third generation (G-DDR-III) have improved performance. According to the G-DDR-III specification, it is now permissible to send series of write commands to the graphics memory, with at least one “NOP command” (NOP=No Operation) needing to be provided between two successive write commands WR. FIG. 1 shows a flow diagram for G-DDR-III write access in which, for a series of two write commands WR, first of all a first write command WR and then a second write command WR are executed. In this case, WL denotes the write latency.
In the case of a G-DDR-III memory, the burst length is stipulated as 4, that is to say that within a data burst lasting two clock cycles (WL=2) of the clock signal CLK there are four data packets D00-D03, D10-D13 processed in parallel. After the end of a respective write command WR, the counter is at CS=“0” in each case. The write access is controlled by the clock signal CLK or by a control signal WDQS derived therefrom. This control signal WDQS is the data strobe write clock control signal WDQS, subsequently also called the write clock control signal WDQS or the WDQS signal WDQS for short. Upon a first falling edge of the WDQS signal WDQS, the counter is started. This edge of the WDQS signal WDQS is also called the preamble PR. Upon each subsequent rising or falling edge of the WDQS signal WDQS, a respective data packet D00-D03 from a first data burst DB1 is latched, that is to say is written to a buffer store. This means that for a counter reading of “4” the respective last data packet D03 from the first data burst DB1 is latched. The subsequent rising edge of the WDQS signal WDQS, which edge corresponds to the counter reading “5”, is also called the postamble PO. Upon the postamble PO, the counter is reset from “5” to “0”. The counter reading then remains at “0” until a second write command WR is used to signal further write access in order to latch data packets D10-D13 from a subsequent second data burst DB2.
One critical case for the counter arises in the event of write access in which there is respectively just a single NOP command (NOP=No Operation) between two successive write commands WR, that is to say for the command sequence WR, NOP, WR, NOP, etc. Such a sequence with just one NOP command NOP between two write commands WR is subsequently also called a “gapless” write command, since in this case the data from two successive data bursts are intended to be written to the graphics memory in the form of a continuous data stream. FIG. 2 shows a flow diagram to illustrate this critical case in the event of three successive gapless write commands. The problem here is that the respective last rising edge, that is to say the postamble PO, which is associated with the last data packet D03 from the data burst DB1, and the first falling edge, that is to say the preamble PR, which is associated with the first data packet D10 from the subsequent data burst DB2, overlap. This means that it is no longer possible to distinguish clearly between the data packets D00-D03, D10-D13 from two successive data bursts DB1, DB2.
The problem is revealed particularly in the case of the counter or its counter reading. On the basis of the counter reading, the counter would interpret the edge of the WDQS signal WDQS from the second data burst DB2 as a preamble PR in this case, even though the preamble PR from this data burst DB2 had actually already been present one clock cycle previously. Similarly, the counter output signal in the case of the third gapless write command, that is to say in the case of the third data burst DB3, would accordingly be two clock cycles too late. Particularly with a large number of such successive gapless write commands WR, the result is then inevitably an increasing shift in the counter output signal with the result that the individual data packets Dx0-Dx3 from the various data bursts DBx are no longer latched properly and hence can no longer be written to the memory properly.
Published German application for patent No. 10 2004 021 694 A1 describes a method for controlling write access and for handling such conflicts in the case of gapless write commands. This document provides a counter for counting the WDQS edges and also a logic circuit which identifies gapless write commands from the detected command sequences and sets a control signal (or control flag) which indicates the presence of a gapless write command. When the control flag is present, the counter is prompted to count two edges of the WDQS signal fewer than is the case for conventional, that is to say non-gapless, write commands (known as gapped write commands).
However, the problem with this is that this control flag is in sync with the on-chip clock CLK, and the WDQS signal is in sync with the write data DQ. Since the WDQS signal is therefore out of sync with the internal clock signal, there may be a fluctuation between the timing of the WDQS signal and that of the internal clock signal. According to the G-DDR-III specification, the phases of the WDQS signal and of the internal clock signal probably differ by up to half a clock cycle. At operating frequencies for the DRAM semiconductor memory extending into the MHz range, this can also be implemented more or less without difficulty. However, this requirement is a problem for operating frequencies in the high MHz range and from the GHz range onward, since here the difference between the phases of the WDQS signal and of the internal clock signal may become increasingly great. In addition, propagation time differences play an increasing role here.